1. Field of the Invention
The present invention relates generally to a simulation system for a semiconductor device utilizing a computer aided design (CAD). More specifically, the invention relates to a unified process and device simulation system and a simulation method for unitarily performing a process simulation and a device simulation.
2. Description of the Related Art
A most important problem in development of a very large scale integrated circuit (VLSI) element is how to achieve high precision and high efficiency in process and device design. Corresponding to a trend to higher integration density and greater scale, it is becoming essential to introduce a simulation technology employing an electronic computer in a stage of process designing and device designing. As means for performing the simulation, a unified process and device simulation system (hereinafter referred to as "simulator") for process device unitary designing, which unitarily sets process condition of the process designing and the device designing in view of a targeted feature of a final element, has been widely employed. In the recent years, corresponding to down-sizing in the order of sub-micron associating with further higher integration density of the integration circuit, higher precision modeling has been required in simulation. In order to satisfy such requirement, there have been proposed various so-called second-generation unified process and device simulators.
As one example of such type of unified process and device simulators, a simulator proposed in Matsuo et al. "A SUPERVISED PROCESS AND DEVICE SIMULATION FOR STATISTICAL VLSI DESIGN" in "INTERNATIONAL WORKSHOP ON NUMERICAL MODELING OF PROCESS AND DEVICES FOR INTEGRATED CIRCUIT", 1990, pages 59-60 of proceeding of NUPAD 3, employs a two dimensional process simulator, a two-dimensional device simulator and a system control unit called as a supervisor which interprets input data and generates an input parameter through modification of standard data in a library, in place of a simple analysis model or a linear numerical model. In the literature, there has been reported that when the simulator is applied for designing of MOSFET according to 8 .mu.m rule, simulation could be done at higher precision with one fourth of simulation period in comparison with the case where the simple analysis model or the linear numerical model.
A simulation method by the above-mentioned conventional process and device composite simulator for simulating variation of electric characteristic of MOSFET with selecting 1 .mu.m, 2 .mu.m and 3 .mu.m as parameter will be discussed with reference to a flowchart in FIG. 15.
Initially, the process simulation is performed employing a process data and a mask data for ion implantation, deposition, oxidation, diffusion, etching and so forth per every predetermined step length (e.g. 1/100 of the overall length) of a MOSFET corresponding to a channel length of 1 .mu.m (hereinafter referred to as "objective device" (step 1501), by the process simulator. Then, by means of the device simulator, a device simulation was performed in terms of analysis condition of the result of the process simulation and analysis condition, such as bias and so forth (step 1502). Similarly, corresponding to the channel length of 2 .mu.m and 3 .mu.m, the operation of the steps 1501 and 1502 are repeatedly executed. Then, when simulations corresponding to designated three types of channels are all completed, overall simulation is terminated (step 1503).
An example section of the device obtained from the above-mentioned conventional simulation method is shown in FIG. 16.
Namely, by performing the process simulation for the objective device, mesh 200 defining segment blocks to perform simulation as shown in FIG. 16 on the section of the device are set and impurity distribution is calculated on the basis of data for respective segment blocks.
On the other hand, utilizing the result of the process simulation, the device simulation is performed. Then, from the obtained result of process and device composite simulation, the electric characteristic of the MOSFET as the objective device can be obtained (see FIG. 17).
When channel length depending characteristic of the MOSFET is simulated, for example, the process simulation and device simulation have to be repeated for overall length of the MOSFET per every predetermined step length over cycles corresponding to number of variation of the channel lengths. In the above-mentioned example, when a computer having an operation speed of 30 MIPS (million instructions per second) is employed, a required period for the process simulation for one cycle (one channel length) becomes approximately 15 minutes, and a required period for the device simulation for one cycle becomes approximately 18 minutes. In the foregoing example, since the process simulation and the device simulation have to be repeated for three times for three distinct channel lengths, necessary operation period for completing overall simulation becomes approximately 99 minutes.
As set forth above, the above-mentioned conventional simulation method encounters a problem of requiring long period for completing overall simulations as the process simulation and device simulation have to be repeated for overall length of the MOSFET per every predetermined step length over cycles corresponding to number of variation of the channel lengths.